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Data Sheet No. PD60233 revB
IR2277S/IR2177S(PbF)
Phase Current Sensor IC for AC motor control
Features * Floating channel up to 600 V for IR2177 & 1200 V for
IR2277
Product Summary
VOFFSET (max) Vin range Bootstrap supply range Floating channel quiescent current (max) Sensing latency (max) Throughput Over Current threshold (max) IR2277 IR2177 1200 V 600 V 250mV 8-20 V 2.2 mA 7.5 sec (@20kHz) 40ksample/sec (@20kHz) 470 mV
* * * * * * *
Synchronous sampling measurement system High PWM noise (ripple) rejection capability Digital PWM output Fast Over Current detection Suitable for bootstrap power supplies Low sensing latency (<7.5 sec @20kHz) Ratiometric analog output suitable for DSP A/D interface
Description
IR2177/IR2277 is a high voltage, high speed, single phase current sensor interface for AC motor drive applications. The current is sensed by an external shunt resistor. The IC converts the analog voltage into a time interval through a precise circuit that also performs a very good ripple rejection showing small group delay. The time interval is level shifted and given to the output both as a PWM signal (PO) and analog voltage (OUT). The analog voltage is proportional to the measured current and is ratio metric with respect to an externally provided voltage reference. The max throughput is 40 ksample/sec suitable for up to 20 kHz asymmetrical PWM modulation and max delay is <7.5 sec (@20kHz). Also a fast over current signal is provided for IGBT protection.
Package
Typical Connection
(Please refer to Lead Assignments for correct pin configuration. This diagram shows electrical connections only)
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IR2277S/IR2177S(PbF) Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS Vin+ / VinG0 / G1 VCC Sync VRH/VRL Out PO OC dVS/dt PD RthJA TJ TS TL
Definition
High Side Floating Supply Voltage High Side Floating Ground Voltage High-Side Inputs Voltages High-Side Range Selectors Low-Side Fixed Supply Voltage Low-Side Input Synchronization Signal DSP Reference High and Low Voltages Analog Output Voltage PWM Output Over Current Output Voltage Allowable Offset Voltage Slew Rate Maximum Power Dissipation Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) IR2277 IR2177
Min.
- 0.3 - 0.3 VB - 25 VS - 5 VS - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3
Max.
1225 625 VB + 0.3 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 50 250 90 125 150 300
Units
V V V V V V V V V V V/ns mW C/W C C C
-40 -55
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to Vss. The Vs offset rating is tested with all supplies biased at 15V differential.
Symbol
VBS VS Vin+ / VinG0 / G1 VCC Sync fsync PO OC VRH VRL TA
Definition
High Side Floating Supply Voltage (VB- VS) High Side Floating Ground Voltage High-Side Inputs Voltages High-Side Range Selectors Low Side Logic Fixed Supply Voltage Low-Side Input Synchronization Signal Sync Input Frequency IR2277 IR2177
Min.
VS + 8.0 -5 VS - 5.0 Note 1 8 VSS 4 8 -0.3 -0.3 3 VSS -40
Max.
VS + 20 1200 600 VS + 5.0 Note1 20 VCC 20 20 Note 2 Note 2 VCC-2.5 VRH-3 125
Units
V V V V V kHz V V V V C
Using PO Using OUT
PWM Output Over Current Output Voltage OUT Reference High Voltage OUT Reference Low Voltage Ambient Temperature Note 1: Shorted to VS or VB Note 2: Pull-Up Resistor to VCC
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IR2277S/IR2177S(PbF) Static Electrical Characteristics
VCC, VBS = 15V unless otherwise specified. Temp=27C; Vin=Vin+ - Vin. Pin: VCC, VSS, VB, VS
Symbol
IQBS IQCC
Definition
Quiescent VBS supply current Quiescent VCC supply current IR2277
Min.
Typ.
1
Max.
2.2 6 50
Units
mA mA
Test Conditions
fsync = 10kHz, 20kHz fsync = 10kHz, 20kHz VB = VS = 1200V VB = VS = 600V
ILK
Offset supply leakage current IR2177 50
A
Pin: Vin+, Vin-, Sync, G0, G1, OC
Symbol
Vinmax Vinmin VIH VIL Vhy Ivinp Ipu |Vocth| RSync RonOC
Definition
Maximum input voltage before saturation Minimum input voltage before saturation Sync Input High threshold Sync Input Low threshold Sync Input Hysteresis Vin+ input current G0, G1 pull-up Current Over Current Activation Threshold SYNC to VSS internal pull-down Over Current On Resistance
Min.
Typ.
250 -250
Max.
Units
mV mV V V V
Test Conditions
2.2 0.8 0.2 -18 -20 300 6 25 -6 -8 470 12 75
See Figure 1 See Figure 1 See Figure 1 fsync = 4kHz to 20kHz G1, G0 = VB5V
A A mV k
@ I = 2mA See Figure 3
Schmitt trigger
SYNC
Rsync
VIL Vhy
VIH
VSS
Figure 1: Sync input thresholds
Figure 2: Sync input circuit
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IR2277S/IR2177S(PbF)
Pin: PO
Symbol Definition Min. Typ. Max. Units Test Conditions
Rpull-up=500 fsync = 4, 20kHz Vthreshold=2.75V Ext supply=5V (See Figure 6)
VPOs
Input offset voltage measured by PWM output
-50
20
mV
VPOs / Tj VPOs Gp Gp / Tj CMRR PO VPOlin
Input offset voltage temperature drift offset between samples on channel1 and channel2 measured at PO (See Note1) PWM Output Gain PWM Output Gain Temperature Drift PO Output common mode (VS) rejection PO Linearity -10 -38
TBD 10 -40.5 TBD 0.2 0.07 TBD 0.8 1.6 0.2 25 75 0.2 -42.5
V/C mV %/V %/(V*C) m%/V % %/C V %/V Vs-Vss = 0, 600V fsync = 10kHz 10kHz 10kHz OC active (See Figure 4) VCC=VBS= 8,20V @ I = 2mA See Figure 3 fsync = 10kHz See Figure 6 Vin=250mV
Vlin/ Tj PO Linearity Temperature Drift VthPO PO threshold for OC reset
PSRR PO PSRR for PO Output RonPO PO On Resistance
Note1: Refer to PO output description for channels definition
PO or OC
RON
VSS
Internal signal
Figure 3: PO and OC open collector circuit
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IR2277S/IR2177S(PbF)
Pin: OUT, VRH, VRL
Symbol
RREF Vaos Vaos / Tj Vaos Ga Ga / Tj CMRR OUT VOUTlin Vlin / Tj PSRR OUT VOUTl VOUTh
Definition
VRH to VRL input resistance Input offset voltage measured by analog output Input offset voltage temperature drift offset between samples on channel1 and channel2 measured at OUT (Note1) Analog Output Gain Analog Output Gain Temperature Drift Analog Output common mode (VS offset) rejection Out Linearity Out Linearity Temperature Drift PSRR for Analog Output Vout Low Saturation Vout High Saturation
Min.
36 -100
Typ.
Max.
84 50
Units
k mV V / C
Test Conditions
TBD
fsync = 8kHz, 20 kHz Measured by analog output fsync = 8kHz, 20 kHz
-20%
2VR TBD 100 0.3 TBD
+20%
V/V C dB
-1
VR=VRH-VRL=3V
0.7
% %/C
30 0 VRH+0.2
100 50 VRH+0.7
dB mV V
Vs-Vss=0V, 600V fsync = 10kHz fsync = 8kHz, 20kHz fsync = 8kHz, 20kHz VCC= VBS =8V, 20V Vin= -500mV Vin = +500mV
Note1: Refer to PO output description for channels definition
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IR2277S/IR2177S(PbF) AC Electrical Characteristics
VBIAS (VCC, VBS) = 15V unless otherwise specified. Temp=27C.
Symbol
fsync fout BW GD Dmin Dmax tdOCon TOCoff Cload SLOUT tsettl MD SR
Definition
PWM frequency Throughput Bandwidth (@ -3 dB) Group Delay (input filter) Minimum Duty Cycle (Note 1) Maximum Duty Cycle (Note 1) De-bounce time of OC Time to reset OC forcing PO Analog output load capacitor Analog output (OUT) Slew Rate Output settling time (1%) Measure Delay Step response (max time to reach steady state) for PO output Step response (max time to reach steady state) for OUT output PO OUT
Min.
4 8
Typ.
Max.
20 20
Units
kHz ksample/sec kHz s % %
Test Conditions
2 f sync
f sync
1 4 f sync
10 30 2.7 3.5 4.7 0.5 0 0.2 5 50 1 30 0.30 2 f sync
1. 3 f sync
Vin=+Vinmax Vin=-Vinmin See Figure 4 See Figure 4 NOTE 2 Cout 5 nF Cout 5 nF
s s nF V/s s s
0.51 f sync
See s Figure 5 See s Figure 5
SROUT
0.51 + t settl f sync
1 .3 + t settl f sync
Note 1: negative logic, see Figure 4 on page 7 Note 2: Cload < 5 nF avoids overshoot
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IR2277S/IR2177S(PbF)
Figure 4: OC timing diagram
Vmax Vin Vmin SYNC PO SR
(PO full response time)
VRH OUT VRL
SROUT (OUT full response time) Figure 5: timing diagram
MD tsettl
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IR2277S/IR2177S(PbF)
Vmax Vin Vmin SYNC
Supply=5V
PO
GP *VPOs1 20% 20% GP *VPOs0 20% DVPOs= VPOs1-VPOs0 GP *VPOs1 20%
Vth=2.75V GP *VPOs0
Figure 6: offset between two consecutive samples measured at PO
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IR2277S/IR2177S(PbF) Lead Assignments
SOIC16WB
Lead Definitions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol
VCC OUT VSS VRL VRH OC PO Sync NC NC G0 G1 VS VINVIN+ VB Low side voltage supply Analog output Low side ground supply Lower rail of A/D voltage range Higher rail of A/D voltage range Over current signal (open drain) PWM output (open drain) DSP synchronization signal No connection No connection Integrator gain lsb Integrator gain msb High side return Negative sense input Positive sense input High side supply
Description
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IR2277S/IR2177S(PbF) Timing and logic state diagrams description
** See OC and PO detailed descriptions below in this document
Functional block diagram
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IR2277S/IR2177S(PbF)
1
Device Description
A residual offset can be read in PO duty cycle according to VPOs (see Static electrical characteristics). According to Figure 8, it can be assumed that odd cycles are represented by SYNC at high level (let's name channel 1 the output related to this state of SYNC) and even cycles represented by SYNC at low level (channel 2). The two channels are independent in order to provide the correct duty cycle value of PO even for non-50% duty cycle of SYNC signal. Small variation of SYNC duty cycle are then allowed and automatically corrected when calculating the duty cycle using Eq. 1. However, channel 1 and channel 2 can have a difference in offset value which is specified in VPOS (see Static electrical characteristics). To implement a correct offset compensation of PO duty cycle and analog OUT, each channel must be compensated separately.
1.1 SYNC input
Sync input clocks the whole device. In order to make the device work properly it must be synchronous with the triangular PWM carrier as shown in Figure 8. SYNC pin is internally pulled-down (10 k) to VSS.
1.2 PWM Output (PO)
PWM output is an open collector output (active low). It must be pulled-up to proper supply with an external resistor (suggested value between 500 and 10k).
Supply
Vlow Figure 7: PO rising and falling slopes PO pull-up resistor determines the rising slope of the PO output and the lower value of PO as shown in Figure 7, where = RC , C is the total PO pin capacitance and R is the pull-up resistance.
1.3 Over Current output (OC)
OC output is an open drain pin (active low). A simplified block diagram of the over current circuit is shown in the Figure 9. Over current is detected when |Vin|=|Vinp-Vinm|>VOCth. If an event of over current lasts longer than tdOCon, OC pin is forced to VSS and remains latched until PO is externally forced low for at least tOCoff (see timing on Figure 4). During an over current event (OC is low), PO is off (pulled-up by external resistor). If OC is reset by PO and over current is still active, OC pin will be forced low again by the next edge of SYNC signal. To reset OC state PO must be forced to VSS for at least TOCoff. * Autoreset function The autoreset function consists in clearing automatically the OC fault. To enable the autoreset function, simply short circuit the OC pin with the PO pin.
Vlow
Ron = Supply R on + R pull -up
where Ron is the internal open collector resistance and Rpull-up is the external pull-up resistance. PO duty cycle is defined for active low logic by the following formula:
Eq. 1
Dn =
Toff _ cycle _ n +1 Tcycle _ n
PO duty cycle (Dn) swings between 10% and 30%. Zero input voltage corresponds to 20% duty cycle.
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IR2277S/IR2177S(PbF)
Cycle 1 Cycle 2 Cycle 3 Cycle 4
Triangular
SYNC (0)
PO
Toff_cycle1
Tcycle1
Toff_cycle2 Tcycle2 Toff_cycle3
Tcycle3 Toff_cycle4
Dn1 =
Toff _ cycle2 Tcycle1
Dn2 = Tcycle2
Toff _ cycle3
Dn3 =
Toff _ cycle4 Tcycle3
Figure 8: PO Duty Cycle
E xt supply
Level shifter
H igh voltage
V IN + V IN -
Low voltage
S R D
OC V SS
O ver current detection
PO
Figure 9: Over current block diagram
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IR2277S/IR2177S(PbF)
1.4 Analog Output (OUT)
The analog output is internally buffered and capable of driving capacitive loads ranging up to 50nF. VRH and VRL set the dynamic range and gain of OUT pin. Additional circuitry to protect A/D converter input against excessive voltage is not required. Hereafter follow some definitions (see Figure 10 and following). * * Vin=Vinp-Vinm Input referred analog offset (Vaos): It is the input that gives an output that equals
OUT VRH
VRH+VRL 2 VRL VSS Vaos
Figure 10: Input offset definition
Vin
(Vpos if PO is measured instead of OUT)
* *
V RH + V RL (referred to VSS). 2 OUT Gain: It is defined by the ratio Ga= . Vin OUT =
Linearity: It is defined by the maximum difference between the ideal OUT/Vin curve and the measured curve depurated of the offset voltage and the gain error.
OUT VRH
The analog output is also defined by some dynamic characteristics (see figure 8): * * * * Slew Rate (SLOUT). The maximum slope of OUT measured in V/s Settling time (tsettl). Time needed by the analog output (OUT) to reach 90% of final value. Measure delay (MD). It is defined by the time interval between the actual SYNC edge and PO rising edge. Step response (SR). Is the time needed by Output to reach the final value after a step of the input. Is always within the following range:
OUT Ga VRL VSS
Figure 11: Gain definition
Gid
Vin
Vin
OUT VRH
1 1 + MD + t settl SROUT + MD + t settl 2 f SYNC f SYNC
Linearity Error Ga VRL VSS
Figure 12: Linearity error definition
Gid
Vin
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IR2277S/IR2177S(PbF)
1.5 DC transfer functions
The working principle of the device can be easily explained by Figure 13, in which the main signals are represented.
Triangular reference SYNC
Eq. 3
OUT = 2 (VRH - VRL ) Vin +
VRH + VRL 2
The same equation can be referred to VRL, as follows in Eq. 4: Eq. 4
OUT - VRL = 2 (VRH - VRL ) Vin +
OUT VRH
VRH - VRL 2
Vin PO VRH OUT VRL
(VRH+VRL)/2
Figure 13: Main current sensor signals and outputs PWM out (PO pin) gives a duty cycle which is inversely proportional to the input signal while the OUT pin gives the analog converted output. Eq. 2 gives the resulting Dn of the PWM output (PO pin): Eq. 2 Dn = 20% - 40 where Vin = Vinp-Vinm
PO duty cycle 30% 25% 20% 15% 10% Vin VRL
-250mV -200mV -100mV 100mV 200mV 0mV
Vin
250mV
Figure 15: ideal OUT/Vin transfer function
% Vin V
Figure 14: PO Duty Cycle (Dn) The Voltage-to-Time conversion (Vin to PO) must be reconstructed (see Functional Block Diagram) to give an analog voltage output at OUT pin. OUT pin swings from VRL to VRH, so the analog output (referred to VSS) follows Eq. 3: 14 www.irf.com
IR2277S/IR2177S(PbF)
Filter AC characteristic
IR2177/2277 signal path can be considered as composed by three stages in series (see Figure 17). The first two stages perform the filtering action. Stage 1 (input filter) implements the filtering action originating the transfer function shown in Figure 18. The input filter is a self-adaptive reset integrator which performs an accurate ripple cancellation. This stage extracts automatically the PWM frequency from Sync signal and puts transmission zeros at even harmonics, rejecting the unwanted PWM noise. The following timing diagram shows the principle by which even harmonics are rejected (Figure 16). As can be seen from Figure 18, the odd harmonics are rejected as a first order low pass filter with a single pole placed in fPWM. The input filter group delay in the pass-band is very low (see GD on AC electrical characteristics) due to the beneficial action of the zeroes. The second stage samples the result of the first stage at double Sync frequency. This action can be used to fully remove the odd harmonics from the input signal. To perform this cancellation it is necessary a shift of 90 degrees of the SYNC signal with respect to the triangular carrier edges (SYNC2). The following timing diagrams show the principle of odd harmonics cancellation (Figure 19), in which SYNC2 allows the sampling of stage 1 output during odd harmonic zero crossings. Odd harmonic cancellation using SYNC2 (i.e. 90 degree shifted SYNC signal) signal will introduce Tsync/4 additional propagation delay. Anther way to obtain the same result (odd harmonics cancellation) can be achieved by controller computing the average of two consecutive PO results using SYNC1 (SYNC is in this case aligned to triangular edges, i.e. 0 degree shift). This method is suitable for most symmetric (center aligned) PWM schemes. For this particular PWM scheme another suitable solution is driving the IR2x77 with a half frequency SYNC signal (fsync=fPWM/2). In this case the cut frequency of the input filter is reduced by half allowing zeroes to be put at fPWM multiples (i.e. even and odd harmonics cancellation, no more computational effort needed by the controller).
Figure 16: Even harmonic cancellation principle
Figure 17: Simplified block diagram 15 www.irf.com
IR2277S/IR2177S(PbF)
Figure 18: Input filter transfer function (10 kHz PWM)
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IR2277S/IR2177S(PbF)
Switching level Triangular
Phase voltage Phase current Current Mean Fundamental harmonic Third harmonic Stage 1 input: Input signal components (1st and 2nd harmonic only)
Fundamental harmonic Third harmonic
Stage 1 output
SYNC 1 Error SYNC 2
Sampling instant Sampling instant
Figure 19: Even harmonic cancellation principle
1.6 Input filter gain setting
G0 and G1 pins are used to change the time constant of the integrators of the high side input filter. To avoid internal saturation of the input filter, G0 and G1 must be connect according to SYNC frequency as shown in Table 1. A too small time constant may saturate the internal integrator, while a large time constant may reduce accuracy. G0 and G1 do not affect the overall current sensor gain. f PWM G0 G1 > 16 kHz * VB VB 16 / 10 kHz VS VB 10 / 6 kHz VB VS < 6 kHz VS VS * 40 kHz Table 1: G0, G1 gain settings
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Sizing tips
2.1 Bootstrap supply
The VBS1,2,3 voltage provides the supply to the high side drivers circuitry of the IR2277S/IR2177S. VBS supply sit on top of the VS voltage and so it must be floating. The bootstrap method to generate VBS supply can be used with IR2277S/IR2177S current sensors. The bootstrap supply is formed by a diode and a capacitor connected as in Figure 20.
Figure 20: bootstrap supply schematic 17 www.irf.com
IR2277S or IR2177S
IR2277S/IR2177S(PbF)
This method has the advantage of being simple and low cost but may force some limitations on dutycycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations. high side freewheeling diode get forwarded biased ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected
VBS = VCC - VF
ILOAD > 0; the load current flows through the freewheeling diode
Bootstrap capacitor sizing
Given the maximum admitted voltage drop for VBS, namely VBS, the influencing factors contributing to VBS decrease are: - - - - Floating section quiescent current (IQBS); Floating section leakage current (ILK) Bootstrap diode leakage current (ILK_DIODE); Charge required by the internal level shifters (QLS); typical 20nC - Bootstrap capacitor leakage current (ILK_CAP); - High side on time (THON).
V BS = VCC - VF + VFP
In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up. b) Bootstrap Resistor A resistor (Rboot) is placed in series with the bootstrap diode (see Figure 20) to limit the current when the bootstrap capacitor is initially charged. We suggest not exceeding some Ohms (typically 5, maximum 10 Ohms) to avoid increasing the VBS time-constant. The minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time-constant. c) Bootstrap Capacitor For high THON designs where an electrolytic tank capacitor is used, its ESR must be considered. This parasitic resistance develops a voltage divider with Rboot generating a voltage step on VBS at the first charge of bootstrap capacitor. The voltage step and the related speed (dVBS/dt) should be limited. As a general rule, ESR should meet the following constraint:
ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient solution). Then we have:
QTOT = QLS + ( I QBS + + I LK + I LK _ DIODE + I LK _ CAP ) THON
The minimum size of bootstrap capacitor is then:
C BOOT min =
QTOT V BS
ESR VCC 3V ESR + RBOOT
Parallel combination of small ceramic and large electrolytic capacitors is normally the best compromise, the first acting as fast charge tank for the gate charge only and limiting the dVBS/dt by reducing the equivalent resistance while the second keeps the VBS voltage drop inside the desired VBS. d) Bootstrap Diode The diode must have a BV> 600V (or 1200V depending on application) and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to VCC supply.
Some important considerations
a) Voltage ripple There are three different cases making the bootstrap circuit get conductive (see Figure 20) ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon
VBS = VCC - VF - VCEon
In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off the Vs node is pushed up by the load current until the 18
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IR2277S/IR2177S(PbF) 3 PCB LAYOUT TIPS
3.3 Antenna loops and inputs connection
Current loops behave like antennas able to receive EM noise. In order to reduce EM coupling loops must be reduced as much as possible. Figure 21 shows the high side shunt loops. Moreover it is strongly suggested to use Kelvin connections for Vin+ and Vin- to shunt paths and starconnect VS to Vin- close to the shunt resistor as explained in Fig. 22.
3.1 Distance from H to L voltage
The IR2277S/IR2177S package (wide body) maximizes the distance between floating (from DCto DC+) and low voltage pins (VSS). It is strongly recommended to place components tied to floating voltage in the respective high voltage portions of the device (VB, VS) side.
3.2 Ground plane
Ground plane must NOT be placed under or nearby the high voltage floating side to minimize noise coupling.
VB
VB VS V in V in +
VS VinVin+
Antenna Loop
Figure 22: Recommended shunt connection Figure 21: antenna loops
3.4 Supply capacitors
The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic traces inductance/resistance
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IR2277S/IR2177S(PbF) Case Outline
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 This part has been qualified for the Industrial Market Data and specifications subject to change without notice. 8/18/2005
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